olofk/wb_intercon

Wishbone interconnect utilities

wb_intercon

Wishbone interconnect utilities

Files

• wb_mux.v Wishbone multiplexer
• wb_arbiter.v Wishbone round-robin arbiter
• wb_data_resize.v Converts 32-bit accesses from master to 8-bit slaves
• wb_upsizer.v Converts accesses from a master to a slave with N times wider data path

wb_intercon also implements a FuseSoC generator called wb_intercon_gen. More info and usage can be found by running fusesoc gen show wb_intercon_gen once wb_intercon is added to the FuseSoC library

The generator can also be run manually. There is an example configuration provided to test this. Run python sw/wb_intercon_gen2.py example/config.yml to generate a new interconnect.

wb_intercon's Issues

verilog_utils.vh is missing

The header verilog_utils.vh is included in many rtl files, but is apparently not in the git repository.

I think it is required at least for ff1 in wb_mux.v.

Explicitly declare datatype of ports in wb_intercon.v

Hi,

I have run into a problem when compiling the veerwolf EL2 project in Intel Quartus Prime Pro. It will complain that the input and output ports of wb_intercon.v do not have explicit datatypes and will not pass synthesis. I think it's because I am using default_nettype none in the top-level module.

Wouldn't it be more "correct" to be explicit with the datatypes of the ports anyway?

Updated verilog-arbiter

Please update core file to include a new version of https://github.com/bmartini/verilog-arbiter. This update addresses warning generated by verilator and quartus. May want to use update wb_mux.v.