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Home Page: http://systemrdl-compiler.readthedocs.io
License: MIT License
SystemRDL 2.0 language compiler front-end
Home Page: http://systemrdl-compiler.readthedocs.io
License: MIT License
In https://github.com/SystemRDL/systemrdl-compiler/blob/master/docs/model_structure.rst the text says:
addrmap top {
my_reg_t A;
my_reg_t B[4];
};
but then in the picture underneath it, it shows:
A B
(reg) (reg)
dim=[4]
Seems to be a mismatch about whether A
or B
is using an array?
I've tried annotating elements with external and while this is accepted by the parser the following visitor gets None
for all nodes. I've tried putting external
(or internal
) on the component def, an instance of an anon def, and on an explicit instance. All the same.
class RTLListener(RDLListener):
def __init__(self):
pass
def enter_Component(self, node):
print(node.inst.external)
As an aside the parser rejects this. Admittedly a weird thing to do, but I think it's legal.
external reg {
field {} f;
} external r;
The SystemRDL 2.0 spec goes at great lengths to describe how component type names are uniquified when parameters get overridden (5.1.1.4). Unfortunately the spec falls short when it comes to dynamic property assignments.
Dynamic property assignments have the capacity to override a component instance's internal definition, and therefore break the ability for a user to distinguish type equivalence based on the type name alone.
reg my_register { /* .... */ };
my_register A;
my_register B;
B -> accesswidth = 8;
// B and A are no longer equivalent types, yet they have the same type name!!!
Proposal is to extend the semantics described in 5.1.1.4 to also include situations where a dynamic property assignment changes a type's definition.
In the above example, the type name of B should get normalized from my_register
to something like my_register_accesswidth_8
Here is example 2 from section 15.2.2 of the SystemRDL 2.0 spec:
enum myEncoding {
alpha = 1'b0;
beta = 1'b1;
};
property my_enc_prop {
type = myEncoding;
component = field;
default = beta;
};
addrmap top {
reg {
field { my_enc_prop = alpha ; } f ;
} regA ;
} ;
When I try compiling that, I get an error:
uarch/lib/registers/foo.rdl:8:12: fatal: Reference to 'beta' not found
default = beta;
^^^^
I'm extremely interested in having this functionality of user-defined properties which are enumerated types.
define
, ifdef
, ifndef
, etc.. are not implemented and are of the few remaining items.
Calling str() on RDL types results in python's default behavior which is pretty boring: <systemrdl.rdltypes.substruct object at 0x7f9cda202898>
Implement the __repr__()
method to pretty-print objects to make debug easier:
<systemrdl.component.Reg (type_name) at 0x####>
<systemrdl.node.RegNode (path.to[42].this_reg) at 0x####>
<struct 'my_struct_t' (foo, bar, baz) at 0x####>
I wanted to put in a request for support of heterogeneous-arrays.
The use case that I am running into is arrayed registers that have different reset values.
I would also be curious about any other workarounds, as all I can think to do right now is use preprocessing to unroll the arrayed registers but that has plenty of negative consequences.
The version of systemrdl-compiler is 1.71, a Error:
error: Property 'donttest' expects a boolean for non-field types. Got an integer in 'HPS_PAGE' } HPS_PAGE @ 0x008;
my rdl code is:
reg HPS_PAGE { desc = "Provides visibility of the page for host accesses to HPS. Previously this was a configurable value but is now fixed at FPGA image compile time"; donttest = true; // exclude from plain simple hw register test stat_f hpsPage[31:21]; hpsPage->desc = "If applicable, the address presented to the ARM interface will be prepended by this value."; } HPS_PAGE @ 0x008;
This is a chicken and egg problem. I'd like a field's reset value be the compiler-calculated address of another register. Is this possible?
I have implemented tree-sitter
parser grammar for SystemRDL 2.0 here: https://github.com/drom/tree-sitter-systemrdl
And syntax highlighter for Atom base on tree-sitter-systemrdl
: https://github.com/drom/language-systemrdl
I was wondering if you have any interest in trying it or/and moving into SystemRDL
org?
Hi,
I'm currently writing a JSON exporter for My designs. I have based my script on the Listener and Walker that are given with the RDL compiler.
The issue is that whenever i'm trying to run the code on an address map, it seems that only the last of each component of the design is visited and transformed into a dictionary (register/field/etc). Maybe I'm missing something.
Would be great to have some advise. Here's the code:
import json
import compilation
from systemrdl import RDLListener
from systemrdl import RDLWalker
from systemrdl.node import AddrmapNode, RegNode, AddressableNode
class JSONListener(RDLListener):
def __init__(self,mydict):
super().__init__()
self.main_dict =mydict
main_dict['Address Map']=None
def enter_Addrmap(self, node):
map_size = node.size
map_name = node.inst_name
if isinstance(node,AddrmapNode):
map_address_absolute=node.absolute_address
map_address_offset=node.address_offset
addrmap_dict = {'Addressmap Name': map_name,
'Map Size': map_size,
'Map offset address': map_address_offset,
'Map absolute address':map_address_absolute,
}
main_dict['Address Map']=addrmap_dict
def enter_Field(self, node):
bit_range_str = "[%d:%d]" % (node.high, node.low)
sw_access_str = node.get_property("sw").name
hw_access_str = node.get_property("hw").name
design_params = node.get_property("design_params")
field_width = node.width
field_dict= {'sw': sw_access_str,
'hw': hw_access_str,
'bit range': bit_range_str,
'field width': field_width,
'design params': design_params}
main_dict['Address Map']['Registers']['Fields']=field_dict
def enter_Reg(self, node):
reg_dict={}
if isinstance(node,RegNode):
reg_dict.update([('Reg', node.get_path_segment())])
reg_size = node.size
reg_address_absolute=node.absolute_address
reg_address_offset=node.address_offset
reg_dict.update([('Reg Size', reg_size),
('Address Offset', reg_address_offset),
('Address Absolute', reg_address_absolute),
('Instantiated From',node.orig_type_name),
('Fields',None)])
main_dict['Address Map']['Registers']=reg_dict
walker = RDLWalker(unroll=True)
main_dict={}
listener = JSONListener(main_dict)
walker.walk(compilation.root, listener)
print(json.dumps(main_dict))
My thought was to use the Listener in order to create a dictionary that will be nested to an upper-level dictionary. Thus, creating a modular data structure.
Thanks in advance. You're doing a great job!
SystemRDL 2.0's constraints is the last major feature that is currently unimplemented. Currently, any RDL that contains a constraint block will fail to compile.
After installing the library, I am trying to run the sample code.
From the repository root folder:
$ examples/print_hierarchy.py
Traceback (most recent call last):
File "examples/print_hierarchy.py", line 11, in <module>
from systemrdl import RDLCompiler, RDLListener, RDLWalker, RDLCompileError
File "/root/my/systemrdl-compiler/examples/../systemrdl/__init__.py", line 2, in <module>
from .compiler import RDLCompiler
File "/root/my/systemrdl-compiler/examples/../systemrdl/compiler.py", line 5, in <module>
from . import messages
File "/root/my/systemrdl-compiler/examples/../systemrdl/messages.py", line 12, in <module>
from .preprocessor.preprocessor import PreprocessedInputStream
File "/root/my/systemrdl-compiler/examples/../systemrdl/preprocessor/preprocessor.py", line 11, in <module>
from .. import messages
ImportError: cannot import name 'messages'
Is this a configuration issue or a bug in the sample code?
Commit id: a130367
Hi,
I think there is a problem with line/column coordinates translation. The example attached below should fail due to missing semicolon. But the message printer would print something like:
examples/example_02/aaa.rdl:3:17: error: missing ';' at '}'
* 4
^
I changed this line:
To:
pl_seg.start, pl_seg.end, pl_seg.file_pp.path,
I did not follow the full consequences of this change but at least I am getting correct message:
examples/example_02/bbb.rdl:5:4: error: missing ';' at '}'
} CONTROL;
^
File
aaa.rdl
(it looks so, because I wanted to have 20 characters per row):`include "bbb.rdl"// /* 3 * 4 * 5 * 6 * 7 * 8 * 9 * 10 * 11 * 12 * 13*/
File
bbb.rdl
:addrmap SYSTEM { reg { field { } A } CONTROL; };
Hello again,
I think I have found one breaking change (one of my RDL description file did not compile):
I guess this is a semantic check against 9.6.1.g. Shouldn't it actually be node.get_property('reset') != 0
?
I can't load Perl modules with "use" or "require", then I get a Perl syntax error.
atxmega_spi.rdl:1:0: error: Encountered a Perl syntax error while executing embedded Perl preprocessor commands:
'require' trapped by operation mask at (eval 5) line 1, <> line 8.
<% use strict; %>
The system environment variables are also not accessible. Do the Perl preprocessor need to run in a Safe compartment, if not just use eval($miniscript);
else please add possibility to load files and access environment, by adding this.
https://github.com/SystemRDL/systemrdl-compiler/blob/master/systemrdl/preprocessor/ppp_runner.pl line 35.
# Run miniscript in restricted context
my $compartment = new Safe;
$compartment->permit(':load'); # permit to load Perl modules
$compartment->share_from('main', [
'%ENV', # share environment
'rdlppp_utils::emit_ref',
'rdlppp_utils::emit_text'
]);
$compartment->reval($miniscript);
I installed the library using the recommended command, that is:
python3 -m pip install systemrdl-compiler
However, I got the following error:
Traceback (most recent call last):
File "./print_hierarchy.py", line 11, in <module>
from systemrdl import RDLCompiler, RDLListener, RDLWalker, RDLCompileError
File "/root/my/systemrdl-compiler/examples/../systemrdl/__init__.py", line 2, in <module>
from .compiler import RDLCompiler
File "/root/my/systemrdl-compiler/examples/../systemrdl/compiler.py", line 3, in <module>
from antlr4 import CommonTokenStream
File "/usr/local/lib/python3.4/dist-packages/antlr4/__init__.py", line 5, in <module>
from antlr4.CommonTokenStream import CommonTokenStream
File "/usr/local/lib/python3.4/dist-packages/antlr4/CommonTokenStream.py", line 33, in <module>
from antlr4.Lexer import Lexer
File "/usr/local/lib/python3.4/dist-packages/antlr4/Lexer.py", line 12, in <module>
from typing.io import TextIO
ImportError: No module named 'typing'
The fix is trivial, but all the dependencies should be installed automatically:
python3 -m pip install systemrdl-compiler
Colorama isn't working properly from Windows cmd shell
Antlr parser seems to default to opening files in ASCII mode.
Results in stacktrace when a non-ascii character is encountered.
Should use UTF-8 by default.
Documentation does not mention anything about how structs work
Hello,
I have read in the Systemrdl documentation about singlepulse and onwrite field's software access properties and for me it seems that if you activate the singlepulse property in a field you couldn't have an onwrite property in the same field. Because both of them change the content of the field.
I was playing around with the systemrdl-compiler and it seems that It is allowed to have both properties specified in the same field. Example:
field Fld4{onwrite = wclr;
singlepulse = true;
}
I am wondering if this is the correct behaviour or the compiler shouldn't allowed this.
Thank you very much.
Laura.
I'm getting the following error when using Perl packages that use the Perl module Exporters.
test.rdl: fatal: Encountered a Perl syntax error while executing embedded Perl preprocessor commands:
'sort' trapped by operation mask at /usr/share/perl5/vendor_perl/Exporter/Heavy.pm line 190, <> line 4.
Compilation failed in require at /usr/share/perl5/vendor_perl/Exporter.pm line 16, <> line 4.
BEGIN failed--compilation aborted at (eval 5) line 1, <> line 4.
Could the Perl safe compartment in the Perl preprocessor be expanded to permit sort
?
I would like to import the variable names into the namespace instead of referencing the package like this $parameters::top
below is a short example as an illustration.
parameters.pm
package parameters;
use Exporter qw(import);
our @EXPORT = qw($top);
our $top = "MyTop";
test.rdl
<% use parameters; %>
addrmap <%=$top%> {
reg {
field {} myfield;
} myreg;
};
With:
Name: systemrdl-compiler
Version: 1.0.0
And the following test case:
addrmap test {
default regwidth = 8;
reg reg1_t {
field {} FIELD1[7:0];
};
reg reg2_t {
field {} FIELD2[7:0];
};
regfile file_t {
reg1_t REG1 @ 0x0;
reg2_t REG2 @ 0x8;
};
file_t FILE1 @ 0x10;
file_t FILE2 @ 0x11;
};
I would expect this to elaborate with four registers:
However, I get the following error:
rdl/test.rdl:14:9: error: Instance 'FILE2' at offset +0x11:0x19 overlaps with 'FILE1' at offset +0x10:0x18
file_t FILE2 @ 0x11;
^^^^^
error: Elaborate aborted due to previous errors
The validator treats the regfile
as a contiguous address space that isn't allowed to overlap. However, while the SystemRDL spec states that registers may not (generally) overlap (10.1.h), I can't find anything that states that regfile
s may not do so. It seems like as long as the resulting registers meet the constraints in 10.1, than this construction should be valid. (There may be something that I'm missing here though.)
(My current workaround is to just ditch the regfile
and instantiate the registers directly.)
I was looking at the user defined properties and by the UDP tests and examples it is quite clear how to check a UDP value on an instance. However, I was wondering whether there is built-in mechanism to query all the UDPs (and their attributes) that are defined within a SystemRDL file?
I also would like to point out one minor inconsistency I stumbled upon. The following code:
property bool_prop {type = boolean; component=field; default=false;};
addrmap test {
reg {
field {
bool_prop;
} FIELD[4] = 0;
} TEST @ 0x0;
};
would return 0
when doing a print(node.get_property("bool_prop"))
on the Python side (and 1
when the default is set to true
. However, when the UDP value is set in the field definition:
field {
bool_prop=true;
} FIELD[4] = 0;
the same query returns True/False
. It is no big deal, equality checks work just the same, just thought I'd let you know.
When the Node.get_rel_path() function was originally implemented, I decided to denote parent references using the ^
operator. One oversight was that these get generated without hierarchy separators. For example, a relative path that traverses upwards:
foo.bar.baz -> foo.abc.def = "^^abc.def"
This behavior creates an inconsistency in relative path semantics. Instead, relative paths through parents ought to be generated as follows:
foo.bar.baz -> foo.abc.def = "^.^.abc.def"
The new parent reference style provides clear separation of hierarchy operations, and will make path parsing more straightforward.
This code takes a RuntimeError trying to validate the RHS as an int or field reference.
enum test_e {
VAL0 = 0;
VAL1 = 1;
};
addrmap test_a {
reg {
field {
encode = test_e;
reset = test_e::VAL1;
} test_f;
} test_r;
};
Interestingly making the RHS an expression test_e::VAL1 + 0
forces it to be evaluated down to an int before the validation check is done and works. Which is an odd looking but effective workaround.
Add the following mechanisms to the Node API:
get_properties()
is returning an explicitly assigned value, or an implicit default.Given this code the fields should have a width of 4. Instead they are taking the default value of the enclosing regfile (i.e. 2)
addrmap nested {
reg r1 #(longint unsigned WIDTH=1) {
field {} f[WIDTH];
};
regfile rf1 #(longint unsigned WIDTH=2) {
reg r2 #(longint unsigned WIDTH=3) {
field {} f[WIDTH];
} #(.WIDTH(WIDTH)) r_inst1;
r1 #(.WIDTH(WIDTH)) r_inst2;
};
rf1 #(.WIDTH(4)) rf_inst;
};
(Discovered when experimenting with @sjalloq's testcase in #34)
When tab characters are printed to the terminal for error message context, the indicator line is doesn't account for the tab width, resulting in it being mis-aligned:
tab_indent.rdl:15:1: fatal: Unrecognized property 'badinput2'
badinput2;
^^^^^^^^^
Never noticed this since my text editor uses space indentation :-).
Since tab-width will render differently depending on the terminal, sanitize whitespace in the context output, and adjust the underline accordingly.
I am intrigued by your comment in #11 about exporters (HTML, IP-XACT).
Wanted to see what your thoughts are about having a JSON exporter? My interest in this would be to then be able to use that JSON with a template engine to export other formats (doc, sw, uvm).
compiler does not require it, but other projects such as @eruanno123's register_compiler
may find this helpful.
By default message printer shall suppress these.
Hi.
So far, I've been using the following script in order to elaborate the design, assuming that the function gets a file with a list of .rdl files:
def compiling_file(input_files):
# Collect input files from the command line arguments: input_files=sys.argv[1:].
# Now, the wrapping script collects the files from the command line and pass it as a list to the compiling_file func.
#print(input_files)
incdir = os.getcwd() # addition for compiling more than one file
# Create an instance of the compiler
rdlc = RDLCompiler()
rdlc.define_udp("design_params", str, [Addrmap, Regfile, Field], None)
roots=[]
try:
# Compile all the files provided
for input_file in input_files:
rdlc.compile_file(input_file, incl_search_paths=[incdir])
# Elaborate the design
roots.append(rdlc.elaborate())
return roots
except RDLCompileError:
# A compilation error occurred. Exit with error code
sys.exit(1)
As you can see, if the function gets multiple files that each one of them contains a list of .rdl files representing addrmaps nested one within another, we'll get a list of RootNodes to work with.
My question- what if I want to pass a list of files containing more than one Root in order to get the roots of all of them and not only the last one?
for example, assume that we have a file containing the following .rdl files:
/current_dir/addrmap1.rdl
/current_dir/addrmap_nested_in_1.rdl
/current_dir/addrmap2.rdl
But, there's no interaction between the firsts and the last one. How can I use the .elaborate() function to get 2 RootNodes?
If an array stride is specified that is smaller than an element's size, validation does not flag this as an error. This allows component addresses to overlap silently.
Currently, the following examples are allowed to compile without error:
addrmap reg_array_overlap {
reg reg32 {
field {} f[32] = 0;
};
reg32 r_array[4] @ 0 += 1; // <--- small array stride causes overlap
};
addrmap regfile_array_overlap {
reg reg32 {
field {} f[32] = 0;
};
regfile rf_100 {
reg32 x @ 0xFC;
};
rf_100 rf_array[4] @ 0x1000 += 1; // <--- small array stride causes overlap
};
To fix, add an additional validation check that verifies that the array stride >= element size
Hi,
Is there an option to assign a parametric value to an instance of components such as regfile
, addressmap or reg, without initializing a value of enum
?
Further more, is it possible to assign a value to a component from another component's property or even defining a variable that will take some value ? for instance:
enum counting{
regnum=a; //some variable with the value 'a' that will be defined later or will take other component's property value (such as size).
};
addrmap TOP{
default regwidth=32;
alignment=64;
reg reg_constructor #(longint unsigned SIZE=5){
field{
name="original name";
desc="some description for this field";
hdl_path_slice='{"rtl_f1_1","rtl_f1_0"};
} f1[1:0];
field{
hdl_path_slice='{"rtl_f2"};
} f2[5:3];
};
reg_constructor reg1[counting::regnum]; //regnum=a;
For now, such code doesn't compile.
Would like to have some advice in this issue.
Thanks!
When the reset is defined as signal reference as shown in example 8.3.2 below, the compiler raises a RuntimeError.
addrmap foo {
reg { field {} a[8]=0; } reg1;
signal { signalwidth=8;} mySig[8];
reg1.a->reset = mySig; // Instead of resetting this field to a constant
// we connect it to a signal to provide an
// External reset value
};
When looking at the validate
method of the Prop_reset
class between lines 586-609 in the systemrdl/core/properties.py
file it seems that the code handles the case when the reset is an int or a field node but passes to the else branch before handling the signal reference case.
Parser fails if the absolute last line of a file is a single-line comment: "//"
Suspect it is because the grammar's SL_COMMENT
token only matches on newlines. It should also match on EOF
Hi
I wanted to try out your compiler but it seems to fall over with the syntax I'm using. So far I've used the Juniper ORDT tools without any issues and they process this RDL fine. It could be the naming convention I used to create easier to read register names using a double underscore. I tend to use "reg_name__field_name" style.
regfile.rdl.pp.final:580:23: error: no viable alternative at input '_sff_irq_flags._irq_3.*' _sff_irq_flags._irq_3.*->enable = _sff_irq_en_flags._irq_en_3.*;
The full RDL is attached.
I'd hate to repeat the spec, but it might be nice to have a list of all the RDL properties embedded in the Sphinx docs.
Only worth the effort if it can be presented in a useful format.
Is it possible to do dynamic filter lists in Sphinx similar to Wikipedia? (Sort alphabetically, sort by component)
Hi,
After reading all the relevant documentation, I still haven't found an explanation how to nest one address map within another one by using the compiler. In order to build more complex register documentation, this feature is needed. In other words, my question is how to 'import' one address map from one SystemRDL file to another one, and compile the new file?
When RDL lexer encounters an unknown character (for example, a rogue '$'), Antlr error listener does not provide an offendingSymbol
token. This results in an ugly stacktrace instead of a pretty-printed error message.
Error listener needs to derive a proper src_ref object in these cases and provide it to the error printer.
Hi,
When defining the swwel
property of a field, the field is returned by the compiler as read-only. Having a write enable signal (even if it is low active) indicates a writable field so this is probably a bug that slipped through. The issue I believe stems from line 526 in the systemrdl/core/elaborate.py
file:
513 if "swwe" in node.inst.properties: 514 swwe = node.inst.properties['swwe'] 515 if isinstance(swwe, rdltypes.ComponentRef): 516 override_to_writable = True 517 elif swwe is True: 518 override_to_writable = True 519 else: 520 override_to_not_writable = True 521 522 elif "swwel" in node.inst.properties: 523 swwel = node.inst.properties['swwel'] 524 if isinstance(swwel, rdltypes.ComponentRef): 525 override_to_writable = True 526 elif swwel is False: 527 override_to_writable = True 528 else: 529 override_to_not_writable = True
I think this was meant to be elif swwel is True
just like for the swwe
property above. Probably the corresponding HW logic unconsciously found its way into the Python code.
@kevbroch reported in SystemRDL/PeakRDL-html#2 that an empty string assigned to a desc property causes a stacktrace.
Origin is in RDLFormatCode html converter.
Assigning desc = "";
result in:
File "/usr/local/lib/python3.6/dist-packages/ralbot/html/exporter.py", line 156, in get_node_html_desc
desc = node.get_html_desc()
File "/usr/local/lib/python3.6/dist-packages/systemrdl/node.py", line 431, in get_html_desc
return rdlformatcode.rdlfc_to_html(desc_str, self)
File "/usr/local/lib/python3.6/dist-packages/systemrdl/core/rdlformatcode.py", line 17, in rdlfc_to_html
+ textwrap.dedent("\n".join(linelist[1:]))
IndexError: list index out of range
Why do you copy the ANTLR license?
I would also like to draw your attention to the fact that the ANTLR license is a modified 3-clause BSD license which protects it author but not its contributors. So is it really required here? If you really need the BSD license I suggest you use the real one, not the ANTLR one.
Built-in mechanism may already exist.
Document or add this as appropriate
Doing things like:
reg data_format { name = "DATA_FORMAT";
desc = "";
field { name = "Arithmetic shift";
desc = "";
onread = rset;
} ash[4:0] = 5'h1f;
};
addrmap example {
signal { signalwidth = 5;} test_sig;
data_format data_format_i;
data_format_i.ash->hwenable = test_sig;
};
results in
fatal: Incompatible assignment to property 'hwenable'
hwenable = test_sig;
^^^^^
This happens for a number of hwaccess properties that according to the SystemRDL 2.0 LRM can take a reference:
I can't find any description in the LRM that states what type of reference these properties should take. A reference to addrmap makes no sense, but a signal reference seems reasonable.
I'm trying to define user-defined properties and use them in multiple files. If I have my user-defined property in one file and if that file is the first in the compile order everything works fine.
However, I would like to include the user-defined property to avoid the requirement to compile it as the first file. To do this I need to make sure it is only included once otherwise, I will get "fatal: Multiple declarations of user-defined property ''". It seems like the Verilog precompiler directive ifndef,
define is not implemented yet, so I tried with the Perl preprocessor.
common.rdl
<% if (!$__common__) { $__common__ = True; %>
property version {type = string; default = "1.0"; component = addrmap|regfile;};
<% } %>
a.rdl
`include "common.rdl"
addrmap a {
version = "2.0";
reg {
field {} foo;
} foo;
};
b.rdl
`include "common.rdl"
addrmap b {
reg {
field {} bar;
} bar;
};
top.rdl
`include "common.rdl"
addrmap top {
a i_a;
b i_b;
};
If this is include twice in the same file every is fine, but if it is inlcuded in seperate files i get "fatal: Multiple declarations of user-defined property 'version'"
I compile it like this:
from systemrdl import RDLCompiler, RDLListener, RDLWalker, RDLCompileError
input_files = ['a.rdl', 'b.rdl', 'top.rdl']
rdlc = RDLCompiler()
try:
for input_file in input_files:
rdlc.compile_file(input_file)
root = rdlc.elaborate()
except RDLCompileError:
raise SystemError
When executing node.get_property() the call returns None unless the property was explicitly given a value despite the property being defined with a default.
Current compiler and RAL model is tailored very specifically around the SystemRDL compilation flow. Needs the flexibility to be able to support importers that read-in other formats (like IP-XACT).
properties.py
- assign_value()
more permissiveI have this code from systemRDL document but cna't get it to compile and generates the following error.
error: Address map 'top' must contain at least one reg, regfile, mem, or addrmap.
fatal: Elaborate aborted due to previous errors
addrmap top {
regfile example {
reg some_reg { field {} a; };
some_reg a @0x0;
some_reg b @0x4;
some_reg c;
some_reg d @0x10;
};
};
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